This invention relates to an apparatus for executing an addition-normalization operation of a floating point calculation, and more particularly relates to a leading one anticipator for anticipating a bit-discard amount resulting from a floating point addition or subtraction and a floating point addition/subtraction apparatus using the leading one anticipator.
Floating point addition and subtraction may cause a case where a subtraction is performed with respect to mantissa values according to a combination of signs of two operands and a addition/subtraction processing. When an absolute value of a difference of exponents of the two operands is not exceeding 1 in the mantissa subtraction, there is a possibility of at least 2 bit-discards of the mantissa value caused. When at least 2 bit-discards is caused, it is necessary to calculate the bit-discard amount for normalizing a result of mantissa subtraction and to normalize the result of subtraction together with the bit-discard amount. However, the addition-normalization is time consuming when the bit-discard amount is calculated and normalized after the result of mantissa subtraction is outputted. It is known that the addition-normalization operation time is reduced by anticipating the bit-discard amount at the normalization prior to or in parallel with the mantissa subtraction by means besides an addition circuit.
As a first conventional example, U.S. Pat. No. 4,926,369 to Hokenek et al. discloses such an apparatus, which is explained below with reference to a drawing. FIG. 8 is a transition diagram showing an algorithm of the leading one anticipator in the first conventional example. The bit-discard amount is anticipated by detecting, from a most significant bit side, a combinational network which processes XOR (P, propagate), AND (G, generate), and NOR (Z, zero) state signals resulting from the comparison of the bits in corresponding bit positions of the two operands in 2's complement notation. First, the state of the most significant bit (G.sub.MSB, Z.sub.MSB, P.sub.MSB) is determined. When the state is G or Z, a signal is produced indicating a shift amount, which amount is counted for each successive state signals detected, as long as the state remains true. When the state becomes false, production of the shift amount signals is halted and an adjustment signal is produced. The adjustment signal is based on a carry from a lower bit at the false bit position, and the state at the false bit position is used to determine whether the result of the addition is positive or negative.
When the state of the most significant bit is P (PMSB), halting of the shift amount signals becomes dependent upon the state of the state signal for the bit position following the false bit position. If the second state (Gj or Zj) at the false bit position is followed by a state signal of the third state (Z when P.fwdarw.G, or G when P.fwdarw.Z), then production of the shift amount signals is continued until the third state becomes false. Otherwise, the shift signals are halted at one bit position following the false bit position. In these cases the adjustment signals is based on the carry from a lower bit at the bit position at which the shift signals are halted, and the state at that position is used to determine whether the result of the addition is positive or negative.
According to the above construction, besides the addition/subtraction circuit, obtained is the bit number of successive zeros or ones from the most significant bit resulting from the mantissa addition/subtraction. In detail, the number of successive zeros is obtained when the result of mantissa addition/subtraction is positive and the number of successive ones in 2's complement notation is obtained when the result of mantissa addition/subtraction is negative.
Another prior art (second conventional example) is disclosed in U.S. patent application Ser. No. 07/825,999 to Miyoshi et al., which is discussed with reference to drawings.
FIG. 9 is a block diagram of a leading one detection circuit in the second conventional example. Reference numeral 804 in the figure indicates a one-bit element of a leading one detection circuit.
A minuend X and a subtrahend Y are inputted to a redundant binary numeral generator 901 per a bit to generate a redundant binary numeral Zsd. Referring to a k-th bit, the redundant binary numeral generator 901 performs a subtraction (minuend Xk-subtrahend Yk) and outputs the redundant binary numeral Zsdk=1, 0 or -1. Then Zsdk is inputted into an intermediate-carry/intermediate-sum generator 902 to generate an intermediate sum Sk and an intermediate carry Ck according to a rule in Table 1, with reference to a 1-bit upper redundant binary numeral Zsdk+1.
TABLE 1 ______________________________________ Zsdk + 1 Zsdk Ck Sk ______________________________________ 1 1 1 -1 1 0 0 0 1 -1 -1 1 0 1 0 1 0 0 0 0 0 -1 0 -1 -1 1 1 -1 -1 0 0 0 -1 -1 -1 1 ______________________________________
Then, a scan-value generator 903 generates a scan value Zk, using the intermediate sum Sk and the intermediate carry Ck-1 from a 1-bit lower bit, according to a rule in Table 2.
TABLE 2 ______________________________________ Ck - 1 Sk Zk ______________________________________ 1 1 1 1 0 1 1 -1 0 0 1 1 0 0 0 0 -1 1 -1 1 0 -1 0 1 -1 -1 1 ______________________________________
At this time, the number of zeros till a leading one from the most significant bit of Z is indicative of a bit shift amount at a normalization or a 1-bit less amount thereof. Therefore the bit shift amount or 1-bit less amount thereof at the normalization can be obtained by inputting Z to a priority encoder. In addition, according to the above construction, besides the addition/subtraction circuit, the bit shift amount or the 1-bit less amount thereof at the normalization is obtained regardless of whether the result of mantissa subtraction is positive or negative.
FIG. 10 is a block diagram of a mantissa calculation part in a floating point addition/subtraction apparatus using the leading one detection circuit in the second conventional example. When a subtraction is performed with respect to two floating point data X, Y each having a mantissa part, an exponent part and a sign part, a digit alignment, a mantissa addition/subtraction and a normalization are performed in this order. Discussed below is the floating point addition/subtraction apparatus using the leading one detection circuit in the second conventional example in FIG. 10.
The digit alignment is performed as below. Exponent parts (Xe, Ye) of two operands are inputted into a subtraction circuit 305, a shift signal generator 304 and a selector 306. At the same time, mantissa parts (1.Xf or 0.Xf, 1.Yf or 0.Yf) of the two operands are inputted into a right/left shifter 301 which shifts the mantissa parts right or left by one bit. The subtraction circuit 305 performs a subtraction with respect to the exponent values Xe, Ye to produce an absolute value and a sign value of (Xe-Ye). At the same time, the shift signal generator 304 detects whether the individual inputted operands are normalized numbers and generates control signals required for shifting respective mantissa values of the two inputted operands right or left, using respective sign values (Xs, Ys) of the operands and a subtraction signal SUB. Based on the control signals from the shift signal generator 304, the right/left shifter 301 shifts the two mantissa values of the operands right or left. Outputs from the right/left shifter 301 are inputted into a swap circuit 302 in which they are swapped in accordance with the sign value of (Xe-Ye) outputted from the subtraction circuit 305 so that the mantissa value of the one operand having an exponent value not greater than that of the other operand is inputted into a right barrel shifter 303 whereas the mantissa value of the latter having a greater exponent value is inputted into an addition/subtraction circuit 307. The right barrel shifter 303 shifts right the inputted value by the absolute value of (Xe-Ye), which is indicative of the difference between the two exponent values of the operands and is outputted from the subtraction circuit 305. The digit alignment is performed in this way.
Secondly, the addition/subtraction circuit 307 performs an addition/subtraction processing and a rounding processing.
Thirdly, normalization processing is explained. In parallel with the second step of the addition/subtraction processing and the rounding processing, the bit-discard amount is anticipated using a leading one detection circuit 311 and a priority encoder 308. The anticipated bit-discard amount is outputted from the priority encoder 308 as Zae.
A left barrel shifter 309 shifts left the output value of the addition/subtraction circuit 307, using the anticipated bit-discard amount Zae outputted from the priority encoder 308, and outputs it. At the same time, the left barrel shifter 309 also outputs a value 1-bit upper than the radix point to a signal line L1. The signal line L1 is "0" when the left shifted value is not normalized, and "1" when the left shifted value is normalized. When the signal line L1 is 0, the anticipated bit-discard amount Zae is 1-bit less than the actual amount, which requires 1-bit left shift. This shift is performed in an alignment circuit 312.
At the same time, the anticipated bit-discard amount Zae is inputted into a subtraction circuit 310, which concurrently performs two subtractions (Ze'-Zae) and (Ze'-Zae-1) to output results to data lines L2, L3. A selector 313 outputs the result of subtraction Ze'-Zae when the value of the signal line L1 is "0" and the result Ze of subtraction of Ze'-Zae-1 when the value thereof is "1" to perform the normalization processing.
In the first conventional example, the number of successive ones from the most significant bit in the 2's complement notation is obtained in case where the result of mantissa addition/subtraction is negative. However, in general, the mantissa value is expressed in an absolute value notation in a floating point format. Therefore, at the conversion, there is a possibility of a 1-bit error caused between the number of successive ones and the bit shift amount at the normalization.
In the second conventional example, the bit shift amount outputted means the bit shift amount at the normalization or a bit shift amount 1-bit less than the bit shift amount at the normalization, which requires to modify the 1-bit error, in addition to a digit alignment of the result of mantissa subtraction with the obtained bit shift amount.